(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to methods and apparatus for removal of copper residue from the edge or periphery of wafers using a process of Chemical and Mechanical cleaning.
(2) Description of the Prior Art
The manufacturing of semiconductor devices typically includes numerous steps of forming device features and of planarizing semiconductor surfaces. The undesired fall-out of many of these steps is that materials that are used during these steps are deposited or migrate to areas from where these material must be removed by processing steps of polishing of surfaces, rinsing of surfaces and the like. All of these steps have as objective to remove contaminants from regions where these contaminants cannot be tolerated and where their presence has a serious negative yield impact.
Chemical Mechanical Polishing (CMP) is a technique that is part of the overall process of creating semiconductor devices. Chemical Mechanical Polishing is a method of polishing materials, such as semiconductor substrates, to a high degree of planarity and uniformity. The process is used to planarize semiconductor slices prior to the fabrication of semiconductor circuitry thereon, and is also used to remove high elevation features created during the fabrication of the microelectronic circuitry on a substrate. One typical chemical mechanical polishing process uses a large polishing pad that is located on a rotating platen against which a substrate is positioned for polishing, and a positioning member which positions and biases the substrate on the rotating polishing pad. Chemical slurry, which may include abrasive materials therein, is maintained on the polishing pad to modify the polishing characteristics of the polishing pad in order to enhance the polishing of the substrate.
The profile of the polishing pad plays an important role in determining good overall polishing results. The polishing pad can, for instance, be profiled thick at the inner diameter of the polishing pad as compared to the outer diameter of the polishing pad and visa versa. The profile of the polishing pad is typically achieved by trial and error and by adjusting the position of a diamond dresser. This method of profiling the polishing pad is destructive, time consuming and causes the loss of the polishing pad. Since this measure of the polishing pad profile can only be performed at the end of the useful life of the polishing pad, the wrong profile can only be detected after the polishing pad has served its useful life.
A polishing pad is typically fabricated from a polyurethane and/or polyester base material. Pads can for instance be specified as being made of a microporous blown polyurethane material having a planar surface and a Shore D hardness of greater than 35 (a hard pad). Other materials used for polishing pads are foam polyurethane, sueded foam polyurathene, unwoven fabric, resin-impregnated unwoven fabric. Semiconductor polishing pads are commercially available such as models IC1000 or Scuba IV of a woven polyurethane material.
In the art of fabricating semiconductors, it is important that the surface of a semiconductor wafer be planar in order to meet the requirements of optical projection lithography. The assurance of planarity is crucial to the lithography process, as consistent and uniform depth of focus of the lithography process across a surface is often inadequate for surfaces that do not have good planarity.
During the fabrication of VLSI and ULSI semiconductor wafers, it is also critically important to use wafers that are free of any surface Cu+ or Cu++ ions since the presence of these impurities has a direct and negative effect on device yield and throughput. It is therefore of extreme importance to use effective means for the control and removal of these impurities from the surface of the wafer since these impurities may, during further high temperature processing steps, diffuse into the wafer surface thereby substantially altering the chemical composition of the wafer. In addition, impurities can be classified as donor or acceptor dopants; these dopants will have an impact on the performance of subsequently produced semiconductor devices. Yet other impurities may cause surface dislocations or internal stacking misalignments or faults further having a negative impact on semiconductor manufacturing yield and cost. It is therefore clear that an effective method must be available to thoroughly clean the surface of the semiconductor substrate from all impurities while this process of removal may have to be repeated at various intervals during the complete processing sequence.
In the conventional approach of applying the process of CMP, the wafer is held in a circular carrier, which rotates. The polishing pad, made from a synthetic fabric, are mounted on a polishing platen which has a flat surface and which rotates. The rotating wafer is brought into physical contact with the rotating polishing pad; this action constitutes the Chemical Mechanical Polishing process. Slurry, which typically includes pH-balanced chemicals, such as sodium hydroxide, and silicon dioxide particles, is dispensed onto the polishing pad typically using a peristaltic pump. The excess slurry typically goes to a drain, which means that the conventional CMP process has an open loop slurry flow and therefore may use and dispense with an excessive amount of slurry that may add significantly to the processing cost. During this process of polishing, rate of slurry flow must also be exactly controlled.
One of the problems that is encountered during manufacturing of semiconductor devices is that the cleaning of the wafer edge has been a relatively neglected area. A conventional CMP process is such that the edge of the wafer, both front and back, are not directly exposed to the CMP process. For these reasons, the edge not only does not get cleaned but it also acts like a trap zone where contaminants easily get trapped and accumulate. It is clear from the above that contaminants that are introduced via the wafer edge can significantly impact device yield. The invention provides a apparatus and method to further clean the wafer edge and to thereby further remove contaminants, particularly copper residue, from the periphery of the semiconductor wafer.
In a typical arrangement of cleaning wafer surfaces, double sided brushes or scrubbers are provided that simultaneously affect both sides of the wafer surface that is being cleaned. The wafer is typically held on a conveyer belt and moved, by the conveyer belt, to the position between the two brushes. In order for the wafer to remain in place while the wafer is being transported and while its surface is being cleaned, an arrangement of rollers is provided that keeps the wafer in one horizontal plane while it moves into and through the cleaning brushes. An arrangement if this type has the drawback that, for the roller to keep the wafer in place in the manner indicated and without causing mechanical damage to the wafer, the force that can be exerted by the cleaning rollers on the surface of the wafer cannot be very high. This results in poor removal of the contaminants from the surface of the wafer. In addition, this configuration cannot reach the bevel area of the wafer to effectively clean this area. Finally, this configuration does not allow for selective cleaning of the wafer edge including the front, bevel and the backside of the wafer. In applying this cleaning technique, the chemical that is used during the cleaning process is exposed to both the edge of the wafer and to the other wafer surfaces. Some of the cleaning chemicals are only desired at the edge of the wafer while they are not desired to be present on the other wafer surfaces and are therefore not used when applying conventional cleaning techniques.
The present invention provides a method and apparatus for cleaning the edge of substrates, including the bevel area if such an area is present.
U.S. Pat. No. 5,976,267 (Culkins et al.) shows 2 pads, one on top and one under the wafer. This appears very close the first embodiment of the present invention. U.S. Pat. No. 5,976,267 however applies a large brush arrangement that is extended over and mounted above the surface of the wafer whereby one of the extremities of this brush has different abrasive action. This as opposed to the first embodiment of the present invention whereby the polishing brush is mounted on the edge of the wafer that is being polished. The second embodiment of the present invention uses a vertically mounted brush as opposed to a brush arrangement under U.S. Pat. No. 5,976,267 whereby the brush is mounted in parallel with the surface that is being cleaned. The vertical mount also acts as an axis arrangement such that the single brush is in contact with the front, bevel and backside of the wafer.
U.S. Pat. No. 5,862,560 (Jensen et al.) shows 2 pads, one on top and one under the wafer. This also appears very close the first embodiment of the present invention. U.S. Pat. No. 5,862,560 addresses a method for mounting and rolling a semiconductor wafer while it is being polished without providing any detail regarding the polishing of the wafer.
U.S. Pat. No. 5,144,711 (Gill, Jr.) shows a cleaning brush for a wafer. U.S. Pat. No. 5,144,711 provides a cleaning brush for cleaning semiconductor surfaces that contains two parallel surfaces whereby the wafer is clamped between these surface in an off-center manner such that at any given time only part of the wafer surface is being cleaned.
None of the methods that are referred to above shows a method that can be applied to clean all three surfaces, that is top, edge and bottom, of a wafer simultaneously. Additionally, none of these methods can apply the cleaning solution exclusively to the edge. Finally, none of the existing methods have a method of delivering chemicals that is a closed loop system, which not only measures the chemical accurately but in addition saves chemicals.
A principle objective of the invention is to provide a method and apparatus for the cleaning of the outer edge of semiconductor substrates.
In accordance with the objectives of the invention a new method and apparatus is provided that can be applied to clean the outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface. After contaminants have been removed in this manner from the surface, the surface can be further cleaned by applying DI water.